Both synchronous and asynchronous RAMs are well known. RAMs are arrays of memory cells that can be read or written to on a set of data lines when addressed on a set of address lines. The state of an asynchronous RAM may transition as soon as any of its inputs change, whereas the state of a synchronous RAM changes only at the transition of a clock signal.
FIGS. 1 and 1a
FIG. 1 shows an asynchronous RAM. When write enable line WE carries a signal that is not active (low in this example), data can be read but not written. When WE is low, an address placed onto address bus ADDRESS(0:n) causes data located in the addressed location to be placed onto data out lines DATA.sub.-- OUT where the data can be read. When write enable line WE carries an active high signal, an address placed onto address bus ADDRESS(0:n) causes data on data-in bus DATA.sub.-- IN to be loaded into the addressed location of asynchronous RAM 105. FIG. 1a shows a timing diagram for signals related to asynchronous RAM 105. The shaded areas indicate times when either a signal is invalid or the state is unimportant. An address ADDRESS(0:n) placed at time T1 causes the addressed data to appear at DATA.sub.-- OUT a short time later, where it can be read. For writing, at time T2, write enable signal WE goes high and causes data on the DATA.sub.-- IN bus to be loaded into the addressed location and to appear on DATA.sub.-- OUT. In order for data to be loaded into the proper memory location, the address must be stable before write enable signal WE goes high. This time difference between T1 and T2 is called the address set-up time and is a requirement made by the chip manufacturer of the user of the chip in order to assure proper writing of data. At time T3, when new data appear at DATA.sub.-- IN, since WE is still high, these new data are loaded into the addressed location of RAM 105 and appear at DATA OUT. At time T4, WE goes low and thus prevents further changes in DATA.sub.-- IN from being loaded or affecting DATA.sub.-- OUT. The time between T3 when new data appear and T4 when WE goes low is the data set-up time, and must be sufficient to assure proper writing of data. The time between T4 and T5 is the data hold time and is again a requirement made by the chip manufacturer in order to assure proper writing. In some circuits the data hold time is designed to be zero or negative. Thus, at time T5 when DATA.sub.-- IN again changes there is no change in DATA.sub.-- OUT. Finally, at time T6, when ADDRESS(0:n) changes, the value on DATA.sub.-- OUT no longer represents the data previously addressed. The time difference between T4 and T6 is called the address hold time, and is another requirement made by the manufacturer. The address and data hold time requirements are not necessarily equal. Finally, the time between T2 and T4 is the write enable pulse width, and is a further requirement made by the IC manufacturer.
This asynchronous RAM has the disadvantages of causing unnecessary switching of DATA.sub.-- OUT (switching consumes power) if DATA.sub.-- IN switches after time T2, and may cause data errors if DATA.sub.-- OUT is read when the incorrect value is present. Also, set-up and hold time requirements may increase cost of a system in which the chip is used.
To avoid such errors and costs, a synchronous RAM can be used. A synchronous RAM receives or provides data only in response to a clock signal. A synchronous RAM can be formed by adding to an asynchronous RAM an input structure for receiving input signals and a clock signal, and providing the input signals to the asynchronous RAM at specified times.
FIGS. 2 and 2a
FIG. 2 shows a synchronous RAM 205. Latches 101 and 102, D flip flop 103 (comprising latches 503 and 504), and delay unit 104 comprise the input structure for providing the signals to asynchronous RAM 105. Delay unit 104 assures that latched write enable signal WE.sub.-- L remains high long enough for data to be written into memory 105, and satisfies the pulse width requirement for write strobe port WS. In response to clock signal K going high, address signals ADDRESS(0:n) and data signals DATA.sub.-- IN are latched into latches 101 and 102 and generate latched output signals LADDR and LDATA. A write enable signal WE is also loaded into flip flop 103 in response to clock signal K going high, and generates latched output signal WE.sub.-- L. When a high signal WE.sub.-- L is applied to the write strobe port WS of asynchronous RAM 105, the signal LDATA is stored in asynchronous RAM 105 in the location specified by LADDR, and can be read as a data out signal DOUT on the DATA.sub.-- OUT bus.
Timing of these signals is shown in FIG. 2a. On the rising edge of clock signal K, write enable signal WE is detected. If write enable signal WE is logical 0, for example, at time T0, a write operation is not enabled, and flip flop 103 maintains its output signal WE.sub.-- L at logical 0 and no values are written into asynchronous RAM 105.
At time T1, while clock signal K is low, write enable signal WE goes high. Bubbles at the clock terminals of latches 101, 102, and 503 (FIG. 2) indicate that when clock signal K is low, latches 101, 102, and 503 are transparent. Thus, address signals ADDRESS(0:n) at the inputs of latch 101 and data signal DATA.sub.-- IN at the inputs of latch 102 are transferred to the latch output lines as signals LADDR(0:n) and LDATA. Similarly, the high WE signal is transferred to the input of slave latch 504.
At time T2, which is before clock signal K goes high, the address and data signals ADDRESS(0:n) and DATA.sub.-- IN become valid, as indicated by the ending of the shaded areas. As LADDR(0:n) becomes valid, the data in the location specified by LADDR(0:n) is output to DATA.sub.-- OUT.
At time T3, clock signal K goes high. This causes the high WE signal to be transferred to WE.sub.-- L and to start a delayed high signal from delay unit 104. The delay is selected to be sufficient for writing to the selected memory cell (or cells). The high K signal also places latches 101 and 102 into a latched state so that further changes in ADDRESS(0:n) and DATA.sub.-- IN do not affect LADDR(0:n), LDATA, or DATA.sub.-- OUT.
A short time later, at time T4, the data output signal DATA.sub.-- OUT reflects the new value written to the RAM, namely LDATA.
Signals LADDR(0:n) and LDATA must remain valid until time T5 when delay unit 104 causes flip flop 103 to be reset and WE.sub.-- L to go low. However, ADDRESS(0:n) and DATA.sub.-- IN need not remain valid since their information has been latched into latches 101 and 102. The high period of clock signal K is required by the chip manufacturer to be no less than the delay of delay unit 104.
At time T6, when clock signal K goes low, signals LADDR(0:n) and LDATA become invalid. Loss of the valid address in turn causes the output data signal DATA.sub.-- OUT to become invalid shortly after time T6. However DATA.sub.-- OUT is valid from time T4 until shortly after time T6, and can be received as a data input signal elsewhere in the circuit during this time window.
FIGS. 3a and 3b
Latches 101 and 102 may be static or dynamic latches. Static latches usually require 5 to 8 transistors for each bit of data whereas dynamic latches require only three transistors per bit. FIGS. 3a and 3b show static and dynamic latches respectively. In FIG. 3a, inverters 602 and 603 are connected into a loop by transistor 604 so that a value can be stored indefinitely in the latch as long as power is applied to the inverters. To write to the static latch, a rising clock signal CLK turns on transistor 601 and turns off transistor 604, thereby allowing an input data value, for example the DATA.sub.-- IN value of latch 102 of FIG. 2, to be applied to node Q,. The complement Qbar is applied to inverter 603. When CLK goes low, transistor 601 turns off, so DATA.sub.-- IN is no longer applied to the static latch and transistor 604 turns on, thus closing the loop and retaining the value. Thus the static latch of FIG. 3a is stable but large.
The dynamic latch of FIG. 3b relies on the capacitance at node Q to retain the state of inverter 602. When CLK goes low, node Q is disconnected from the DATA.sub.-- IN signal. Because of leakage represented by parasitic diode 606 and the subthreshold leakage of transistor 601, this dynamic latch holds the value at Q on the order of a millisecond after CLK is brought low. If CLK remains low for a long enough period, node Q floats to an intermediate value with two negative results: (1) latch data may be lost, and (2) the inverter begins to conduct high current between the positive and ground voltage supplies, which in some cases can destroy an integrated circuit device. In a circuit such as shown in FIG. 2, the write enable signal WE.sub.-- L is high only briefly while new data are being entered into RAM 105, therefore a dynamic latch such as shown in FIG. 3b is appropriate. However, this dynamic latch may not be used when K stays high for an unpredictable duration. In FIG. 2a, the signals LADDR(0:n) and LDATA are shown as becoming invalid before K goes low. To prevent this situation, the IC manufacturer has required users of the IC device to maintain clock signal K high only for brief periods. This requirement has been a burden to system makers using chips having dynamic latches. Using static latches will maintain the latched signals stable indefinitely but the larger area is undesirable if there are many latches.
It would be preferred to continue using dynamic latches rather than the larger static latches but avoid minimum switching speed requirements on a clock signal K for controlling synchronous RAM.